Technology to shrink devices and wire interconnects in order to manufacture integrated circuits seems to improve each year. As the devices and wire interconnects have been shrunk so much, the inherent effect of process variations during manufacturing of integrated circuits is playing an increasingly larger factor in the behavior and performance of a circuit.
To compensate for such behavior, static timing analysis (STA) was used with a corner-based approach. That is, a circuit would be analyzed using a STA tool at different process corners. However, as process technology has made it capable to manufacture even smaller geometries of devices and interconnect, the effect of process variations in the manufacturing process may not be adequately captured with a corner-based static timing analysis.
Additionally, a corner-based static timing analysis may predict worse conditions than actually occur in manufacturing an integrated circuit. This may be particularly the case if all of the parameters are set to worst case in one corner and all are set to best case in another. The corner-based static timing technique can respectively lead to integrated circuit designs which are overly conservative due to the worst case corner and/or may provide overly optimistic timing analysis results due to the best case corner. Additionally, a corner-based static timing analysis is expensive in terms of run-time and/or performance. To perform an exhaustive analysis, the number of times that a corner based static timing analysis is executed can grow exponentially as a function of the number of process parameters considered. The number of corner based static timing analysis runs may be too large to permit computational efficiency.
It is desirable to provide a more accurate timing analysis to avoid over designing an integrated circuit and to reduce the time to design and analyze an integrated circuit prior to manufacturing.